A Self Calibrated Based Clock Generator for DLL

In this paper, a Delay-Locked Loop (DLL) based clock generator is designed which can be used mainly for dynamic frequency scaling. This DLL-based clock generator is found to have low-jitter and can provide the system clock with frequencies in the range of 0.5 to 8 times of reference clock, depending on the workload of the EISC processor. This proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between the delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. Power and delay mismatches are analyzed by using delay calibration method and by using alpha latch instead of delay calibration. It is found that the performance parameters like power and area are better reduced while using alpha latch rather than delay calibration. Index Terms — Calibration, delay-locked loop (DLL), dynamic frequency scaling (DFS), extendable Instruction set computing (EISC).